Re: CCP1 Glitches in noisy environment (RC Tx)

: You have a huge noise there, try to see why. Almost 2Vpp of noise is a
: real mess.
: It's possible that sometime the PWM dutycycle be longer that PWM period?
: Only then the CCP output remains high. Maybe a compiler problem ?

I should have been clearer about the part of the CCP module that I was
using.  I'm using the "compare" rather than the "pwm" part.

I don't think that it is a compiler problem as the effect is random and
nothing else appears to be affected.  I can't see it just jumping off
somewhere else in the program and not having an effect on either the Timer 1
or the CCPR1 register.

I need to look more carefully at the noise on the 5 V section of the
daugther board.  It is buried in the transmitter box and a PIA to get at.
Because the ADCs are noise free, my assumption was that it was fairly noise
free.

How much noise on the power lines is acceptable?

If the noisy supply voltage stays between 2.0 and 5.5 volts, is that OK? Or
does the noise component need to be kept below some value p-p?

Regards,

Gordon Williams


: On 5/12/08, Gordon Williams <g_will@...> wrote:
: > Hi All,
: >
: > I'm having problems tracking down the reason of some glitches occurring
on
: > the CCP1 output and it is driving me a bit crazy.
: >
: > I'm putting some smarts into a basic RC transmitter.  I've replaced the
: > current chip producing the pulse train to the RF section with a daughter
: > board and added a cell phone LCD, some switches and Serial port for
input
: > and output.  The serial port and LCD (spi) work fine and they don't have
any
: > glitches.  The 5 ADC readings for the joysticks (4) and battery voltage
also
: > work well with only 1 bit of noise on a 10 bit reading (referenced to
the
: > power and gnd lines).
: >
: > The PIC that I am using is the 16F886.  Its supply is a 78L05 on the
main
: > board and I have a 10uf Tant and three 0.1uF on the power lines on the
: > daughter board.  The daughter board is single sided with a ground plane
pour
: > under the PIC and every else where I could.  Because I don't have ADC
: > problems or serial or spi errors that noise must be reasonably
constrained,
: > I think.
: >
: > I'm using CCP1 (pin C2) to produce the PPM that goes to the RF section.
It
: > is the standard PPM protocol (each channel pulse is 1 to 2 ms wide
including
: > the following 0.3 ms pulse, repeated every 20ms).
: >
: > Timer1 runs freely.  With a CCP1 interrupt (my only interrupt) I update
: > CCPR1 with the duration until the next transition high or low and the
: > CCP1CON bits to set the next transition in the correct direction.  My
main
: > program clears a flag and that is all.
: >
: > Most of the time it works perfectly and looks like:
: > http://www.cyberus.ca/~g_will/TxGlitch/NoGlitch1.jpg
: >
: > or detail
: >
: > http://www.cyberus.ca/~g_will/TxGlitch/NoGlitch.jpg
: >
: > The receiver pulses for the first 4 channes are shown in the logic
section
: > below.
: >
: > Every 20 to 100 frames on average (sometimes they are consectutive
frames) I
: > get a glitch:
: >
: > http://www.cyberus.ca/~g_will/TxGlitch/Glitch1.jpg
: >
: > or
: >
: > http://www.cyberus.ca/~g_will/TxGlitch/Glitch2.jpg
: >
: > The green lines indicate where the signal should have been.
: >
: > There is a fair bit of noise - about 1.8 volts p-p because the scope
ground
: > was attached to the battery neg lead.  I don't think that my probes are
very
: > well shielded either.  The noise is from the 72 Mhz RF.
: >
: > In each case the low output flips high.  My question is WHY?
: >
: > Timer 1 keeps on rolling as there is no problem with frame spacing or
the
: > width or placement of the next good pulse.
: >
: > CCPR1 is not upset or incorrectly set for the same reasons - because the
: > next good pulse is in the proper location relative to the last good
pulse.
: >
: > The serial and LCD have been comment out.  I'm reading 2 ADC on port A
and
: > 3ADC on port B.  All other pins on ports A,B,C are inputs and some are
: > floating (could this be a problem?)
: >
: > Is there anything else on the chip that may be miss-configured that may
be
: > giving me a problem?
: >
: > The chip docs say:
: > Note: Clearing the CCP1CON register will force
: > the CCPx compare output latch to the
: > default low level. This is not the PORT I/O
: > data latch.
: >
: > But I don't think that this applies to me.  The only time that I do
anything
: > with the CCP1CON is during the long bit in the frame between the pulse
: > series and the glitch doesn't always happen there.
: >
: > It is not read-mod-write ... I'm not writing anything to the port.
: >
: > I read the errata - nothing there indicated a problem.
: >
: > Any ideas what I should be looking at/ trying next??
: >
: > - I guess I should look at the 5 v power going to the chip to see that
it is
: > truly quiet and doesn't have a spike.  Brown out is disabled.
: >
: > - Should set the un-used outputs to either high or low.  - Good right?
: >
: > Funny that it is only affecting one pin that I can see.
: >
: > Looking for suggestions...
: >
: > Regards,
: >
: > Gordon Williams
: >
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