Nabble - MPC500

RE: MPC555 QSPI interrupts

2009-01-08T10:03:53Z

Sorry about the lack of detail as its been a while. Yes, the SPI
interrupt does work, you have to ensure all of the following are valid:

- MSR[EE] bit must be set to allow ext interrupts
- set the local interrupt mask bit within the SPI for the desired
interrupt
- set the priority of the SPI interrupt higher than the current priority
- enable that particular int level in USIU.SIMASK

I'm very rusty on MPC500 family interrupts but pay attention to the
following registers:
- UIMB.UMCR
- MSR[IP] bit allows relocating interrupts.

- Allan

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of blueshawk1952
Sent: Wednesday, January 07, 2009 7:03 PM
To: MPC500@...
Subject: [MPC500] MPC555 QSPI interrupts

I have been trying to get QSPI interrupts to work for quite a while,
following the user manual and the mpc555 interrupts application note,
with no luck. I have put a breakpoint at location 500, where it should
get before vectoring to the ISR, but it never gets there.

Has anyone else been through this, or have any examples of how to do it?

I am transferring data to the device, but I never get an interrupt when
the queue is empty, even though I have followed the 5 steps outlined in
the application note, but no luck.

Larry

[Non-text portions of this message have been removed]

re: MPC5500 Configuration and Initialization

2009-01-07T17:53:05Z

--- In MPC500@..., "stevenaschroeder"
<stevenaschroeder@...> wrote:
>
> I have been experimenting with Freescales, MPC5500 initialization code
> and wonder if someone could clarify a few things for me. Running down
> the list of configuration functions:
>
> cfg_CACHE - If I understand, the cache is not active out of reset, so
> this simply enables it.
>(1) Why wouldn't you want to do this?
you might want to reserve a large chunk of the cache to be used as
SRAM for fast access (like for the stack to improve interrupt
performance).

You may also may want to lock some code into the cache, also for fast
access.

>(2) If
> you know the particular part has cache, is there a need to check
> L1CFG0?
If you are writing your code to be device independent, you may wasnt
to check for the existence of cache or the size of the cache before
you decide how you want it initialized. Thus you could write code that
wants across multiple devices that have different size caches or even
no cache.

>
> cfg_FMPLL - The Reference refers to setting the clock with your final
> values with RFD+1, then reducing RFD after lock. (1) Why would you
> want to set the clock to a series of rates, waiting for locks, such as
> the 132MHz example? (2) What is the significance of inhibiting the
> cache?
you may want to control the ramp of current requirements to reduce the
load on your power supply for peak current changes. you can do this by
ramping the speed up.

>
> cfg_SRAM - To initialize the SRAM's ECC. Not doing this is probably
> bad--more than just loosing ECC, it may flip bits incorrectly on read?
the ECC fields of every SRAM location must be initialized before any
of the SRAM can be used for any purpose.

>
> cfg_FLASH - What has changed at this point to allow less internal
> flash wait states?
the device defaults to the maximum wait states (slow access), since
you device does not know the frequency of the crystal itself. Once you
have the PLL configured to your final system frequency, you can set
the wait states for the flash to the optimum performance settings as
defined in the device data sheet for the sytem frequency chosen.

>
> cfg_MMU - If BAM's flat setup of the MMU is adequate, is there any
> reason to worry about this?
Many people want to change the MMU settings to set change the
protection settings for given areas for specific purposes, such as
disable execution from flash areas that are used to store data (and
not instructions)

>
> Thanks in advance.
> Steve
>

MPC555 QSPI interrupts

2009-01-07T17:03:12Z

I have been trying to get QSPI interrupts to work for quite a while,
following the user manual and the mpc555 interrupts application note,
with no luck. I have put a breakpoint at location 500, where it should
get before vectoring to the ISR, but it never gets there.

Has anyone else been through this, or have any examples of how to do it?

I am transferring data to the device, but I never get an interrupt when
the queue is empty, even though I have followed the 5 steps outlined in
the application note, but no luck.

Larry

RE: Digest Number 1127

2009-01-07T12:53:09Z

Why wouldn't everyone always enable cache?

Sometimes predictability or determinism is more important than average
speed.

If testing and _proving_ consistent behavior is more important than
average throughput (i.e. safety-critical or high-regulated
applications), cache indeterminacy may invalidate all the V&V testing.
"Failure to certify" trumps "performance". Reducing the number of
variables makes thorough testing easier.

1. Suppose you have to prove that you will _always_ meet a certain
deadline (for example in an ISR). If you tested in such a way that the
ISR code was always found in cache, and then in the field it rarely was
not, your test would have passed but the system would have failed.

2. Sometimes in control loops, jitter in a delay can disrupt the
system. A loop that was "slow but steady" could be tuned and behave
predictably. A loop that was sometimes fast and sometimes slow may
behave too unpredictably.

3. Just in general, "determinism" increases confidence. When the "worst
case" is all-important, you need to be sure that your testing and
experience caught all possible worst-cases, so you want as few variables
as possible. In safety-critical apps, you would like the worst-case and
best case to be the same, so you could know that "it will always do
exactly the same thing, and we tested the heck out of that thing".

You might suggest "test with cache turned off and then turn it on in
delivered code", but sometimes "faster" can cause problems not
previously seen - like exposing an unanticipated race condition, or
buffer underflow at "just the wrong time". When safety matters, you
really do have to ship what you tested.

Embedded control apps can have unusual needs.

Rick Corey

Rick Corey | Software Engineer | Crane Aerospace & Electronics | Home:
425-741-5857 |
Desk: 1 425-743-8469 | M: +1 908-887-0722 | F: +1 425-743-8540 |
richard.corey@...
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________________________________

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Subject: [MPC500] Digest Number 1127

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1a.

AN2789 - MPC5500 Configuration and Initialization From: stevenaschroeder

1b.

Re: AN2789 - MPC5500 Configuration and Initialization From: Dobbin Allan

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1a.

AN2789 - MPC5500 Configuration and Initialization
<http://groups.yahoo.com/group/MPC500/message/3975;_ylc=X3oDMTJxOHZibnVs
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Posted by: "stevenaschroeder" stevenaschroeder@...
<mailto:stevenaschroeder@...?Subject=%20Re%3AAN2789%20-%20MPC5500%
20Configuration%20and%20Initialization> stevenaschroeder
<http://profiles.yahoo.com/stevenaschroeder>

Wed Jan 7, 2009 9:23 am (PST)

I have been experimenting with Freescales, MPC5500 initialization code
and wonder if someone could clarify a few things for me. Running down
the list of configuration functions:

cfg_CACHE - If I understand, the cache is not active out of reset, so
this simply enables it. (1) Why wouldn't you want to do this? (2) If
you know the particular part has cache, is there a need to check
L1CFG0?

cfg_FMPLL - The Reference refers to setting the clock with your final
values with RFD+1, then reducing RFD after lock. (1) Why would you
want to set the clock to a series of rates, waiting for locks, such as
the 132MHz example? (2) What is the significance of inhibiting the
cache?

cfg_SRAM - To initialize the SRAM's ECC. Not doing this is probably
bad--more than just loosing ECC, it may flip bits incorrectly on read?

cfg_FLASH - What has changed at this point to allow less internal
flash wait states?

cfg_MMU - If BAM's flat setup of the MMU is adequate, is there any
reason to worry about this?

Thanks in advance.
Steve

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1b.

Re: AN2789 - MPC5500 Configuration and Initialization
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Posted by: "Dobbin Allan" Allan.Dobbin@...
<mailto:Allan.Dobbin@...?Subject=%20Re%3A%20AN2789%20-%20MPC55
00%20Configuration%20and%20Initialization> allandobbin2000
<http://profiles.yahoo.com/allandobbin2000>

Wed Jan 7, 2009 9:54 am (PST)

I am not familiar with any of these specific files, but will try to
answer some from a general perspective:

cache - correct, cache is disabled out of reset. To enable cache you
have to write the L1CSR0 to turn on the cache, plus you have to make
specific memory cachable within its MMU setting - note that some of the
MMU settings already be cachable out of reset. (1) Why would you want
to enable cache - cache is only one access cycle so your code will
executes faster. Note that Idd will increase when you use the cache.
(2) There is no need to check L1CFG0 - this is constant data for each
part in the family and merely confirms the size of the cache.

FMPLL - this allows you to set you sysclk to your desired rate. (1)
Changing PREDIV and MFD forces the PLL to re-lock which means the
frequency swings either side of the final locking frequency. If you are
setting the max sysclk i.e. 132, the sysclk would swing above that value
briefly during the locking phase and its possible the part could fail if
the frequency is too high. To prevent this, you get it to lock with the
post divider (RFD) at +1 (i.e. divide by 2) i.e. 66MHz so that max freq
is not violated. Once the PLL has locked, you set RFD to desired value
to get desired frequency (i.e. 132M) and since the post divider is
outside of the VCO loop, there is no relocking or overshoot during this
second step. (2) can't think of a good reason why cache is inhibited
here.

SRAM ECC - you HAVE to init the SRAM after a power up (not required
after a RESET) by performing a 64-bit write. Failing to do so means
that the 72-bit SRAM word (64-bit data plus 8-bit ECC checksum) has
incorrect checksum and any accesses other than a 64-bit write will cause
it to fail and generate an exception or bus error. Not initialising the
SRAM doesn't mean bits will flip, it means you simply cannot read or
write the SRAM.

cfg_FLASH - the Flash comes out of reset with maximum wait-states.
Refer to the ref manual, but even at max sysclk frequency, maximum wait
states are not required, so to get improved performance from the flash,
you would set the minimum possible wait-states for your operating
frequency.

cfg_MMU - I'm not familiar with the details of the files but reasons for
changing MMU would be to enable cache or VLE for specific regions, to
set memory blocks for external memory or even to re-arrange the entire
memory map to suit your own prefferential memory map if so desired.

- Allan

________________________________

From: MPC500@... <mailto:MPC500%40yahoogroups.com>
[mailto:MPC500@... <mailto:MPC500%40yahoogroups.com> ] On
Behalf
Of stevenaschroeder
Sent: Wednesday, January 07, 2009 11:24 AM
To: MPC500@... <mailto:MPC500%40yahoogroups.com>
Subject: [MPC500] AN2789 - MPC5500 Configuration and Initialization

I have been experimenting with Freescales, MPC5500 initialization code
and wonder if someone could clarify a few things for me. Running down
the list of configuration functions:

cfg_CACHE - If I understand, the cache is not active out of reset, so
this simply enables it. (1) Why wouldn't you want to do this? (2) If
you know the particular part has cache, is there a need to check
L1CFG0?

cfg_FMPLL - The Reference refers to setting the clock with your final
values with RFD+1, then reducing RFD after lock. (1) Why would you
want to set the clock to a series of rates, waiting for locks, such as
the 132MHz example? (2) What is the significance of inhibiting the
cache?

cfg_SRAM - To initialize the SRAM's ECC. Not doing this is probably
bad--more than just loosing ECC, it may flip bits incorrectly on read?

cfg_FLASH - What has changed at this point to allow less internal
flash wait states?

cfg_MMU - If BAM's flat setup of the MMU is adequate, is there any
reason to worry about this?

Thanks in advance.
Steve

[Non-text portions of this message have been removed]

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RE: AN2789 - MPC5500 Configuration and Initialization

2009-01-07T09:54:07Z

I am not familiar with any of these specific files, but will try to
answer some from a general perspective:

cache - correct, cache is disabled out of reset. To enable cache you
have to write the L1CSR0 to turn on the cache, plus you have to make
specific memory cachable within its MMU setting - note that some of the
MMU settings already be cachable out of reset. (1) Why would you want
to enable cache - cache is only one access cycle so your code will
executes faster. Note that Idd will increase when you use the cache.
(2) There is no need to check L1CFG0 - this is constant data for each
part in the family and merely confirms the size of the cache.

FMPLL - this allows you to set you sysclk to your desired rate. (1)
Changing PREDIV and MFD forces the PLL to re-lock which means the
frequency swings either side of the final locking frequency. If you are
setting the max sysclk i.e. 132, the sysclk would swing above that value
briefly during the locking phase and its possible the part could fail if
the frequency is too high. To prevent this, you get it to lock with the
post divider (RFD) at +1 (i.e. divide by 2) i.e. 66MHz so that max freq
is not violated. Once the PLL has locked, you set RFD to desired value
to get desired frequency (i.e. 132M) and since the post divider is
outside of the VCO loop, there is no relocking or overshoot during this
second step. (2) can't think of a good reason why cache is inhibited
here.

SRAM ECC - you HAVE to init the SRAM after a power up (not required
after a RESET) by performing a 64-bit write. Failing to do so means
that the 72-bit SRAM word (64-bit data plus 8-bit ECC checksum) has
incorrect checksum and any accesses other than a 64-bit write will cause
it to fail and generate an exception or bus error. Not initialising the
SRAM doesn't mean bits will flip, it means you simply cannot read or
write the SRAM.

cfg_FLASH - the Flash comes out of reset with maximum wait-states.
Refer to the ref manual, but even at max sysclk frequency, maximum wait
states are not required, so to get improved performance from the flash,
you would set the minimum possible wait-states for your operating
frequency.

cfg_MMU - I'm not familiar with the details of the files but reasons for
changing MMU would be to enable cache or VLE for specific regions, to
set memory blocks for external memory or even to re-arrange the entire
memory map to suit your own prefferential memory map if so desired.

- Allan

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of stevenaschroeder
Sent: Wednesday, January 07, 2009 11:24 AM
To: MPC500@...
Subject: [MPC500] AN2789 - MPC5500 Configuration and Initialization

I have been experimenting with Freescales, MPC5500 initialization code
and wonder if someone could clarify a few things for me. Running down
the list of configuration functions:

cfg_CACHE - If I understand, the cache is not active out of reset, so
this simply enables it. (1) Why wouldn't you want to do this? (2) If
you know the particular part has cache, is there a need to check
L1CFG0?

cfg_FMPLL - The Reference refers to setting the clock with your final
values with RFD+1, then reducing RFD after lock. (1) Why would you
want to set the clock to a series of rates, waiting for locks, such as
the 132MHz example? (2) What is the significance of inhibiting the
cache?

cfg_SRAM - To initialize the SRAM's ECC. Not doing this is probably
bad--more than just loosing ECC, it may flip bits incorrectly on read?

cfg_FLASH - What has changed at this point to allow less internal
flash wait states?

cfg_MMU - If BAM's flat setup of the MMU is adequate, is there any
reason to worry about this?

Thanks in advance.
Steve

[Non-text portions of this message have been removed]

AN2789 - MPC5500 Configuration and Initialization

2009-01-07T09:23:47Z

I have been experimenting with Freescales, MPC5500 initialization code
and wonder if someone could clarify a few things for me. Running down
the list of configuration functions:

cfg_CACHE - If I understand, the cache is not active out of reset, so
this simply enables it. (1) Why wouldn't you want to do this? (2) If
you know the particular part has cache, is there a need to check
L1CFG0?

cfg_FMPLL - The Reference refers to setting the clock with your final
values with RFD+1, then reducing RFD after lock. (1) Why would you
want to set the clock to a series of rates, waiting for locks, such as
the 132MHz example? (2) What is the significance of inhibiting the
cache?

cfg_SRAM - To initialize the SRAM's ECC. Not doing this is probably
bad--more than just loosing ECC, it may flip bits incorrectly on read?

cfg_FLASH - What has changed at this point to allow less internal
flash wait states?

cfg_MMU - If BAM's flat setup of the MMU is adequate, is there any
reason to worry about this?

Thanks in advance.
Steve

RE: Re:Re: problem in running 'Hello_fl' example by codewarrior 8.7

2009-01-06T10:26:30Z

are setting setting up CS0? CS0 acts as a global chip select until OR0
is written and over-rides all other chip selects.

randy.

[Non-text portions of this message have been removed]

RE: Re:Re: problem in running 'Hello_fl' example by codewarrior 8.7

2009-01-06T08:53:14Z

Is EPP an improvement, or were able to connect previously?

Try debugging to see where it fails - 4000, 2000, 1000?
Try increasing the wait states and the burst wait states.
Try changing the address mask in the OR register to see if that helps.

When you enabled the debugger to verify downloads, what addresses
failed?
When you enter at __start and view mixed mode, do you get the correct
opcodes?

May I ask what line of business you are in?

Regards,
Allan

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of F KH
Sent: Tuesday, January 06, 2009 10:26 AM
To: MPC500@...
Subject: [MPC500] Re:Re: problem in running 'Hello_fl' example by
codewarrior 8.7

Thanks for you replies.
I set the parallel port on EPP and it seems OK.
The memory is external SRAM(4 x KM736V987) in address 0x10000000 and CS1
is enabled for it in config file:

; Chip select CS1 - external synchronous burst RAM
writemem.l 0x2fc10c 0xFF800000 ; OR1=0xFF800000
; BSCY
0x#######E = 0x0 - 0-clock burst beat length
; SCY
0x######F# = 0x0 - (2+SCY)*clock = 0 wait
; AM
0xFFFE#### = 0xFFF80000 - 512 kByte
;
= 0xFFF00000 - 1 MByte
;
= 0xFFE00000 - 2 MByte
;
= 0xFFC00000 - 4 MByte
;
= 0xFF800000 - 8 MByte
;
= 0xFF000000 - 16 MByte
writemem.l 0x2fc108 0x10000001 ; BR1=0x10000001
;writemem.l 0x2fc108 0x10000001 ; BR1=0x00000001 relocation to
base address 0x0
; Bit
0x#######1 = 1 - region valid
; Bit
0x#######2 = 0 - burst access enabled
; Bit
0xFFFF#### = 0x1000 - Base address = 0x10000000

I select connect from debug menu and system connected,then in
debug>EPPC>fill memory window set:
Memory Type:32 bit
Memory address:0x10000000
Memory Size:100

and it writes to memory(I can view).But when I check it for Memory size
0x8000 makes error and every thing goes wrong.
I select the checkbox for 'verify memory writes',the verify fails.
PhyCORE has 4M SRAM and i don't know what make this errors?

Best Regards
Farzane

[Non-text portions of this message have been removed]

Re:Re: problem in running 'Hello_fl' example by codewarrior 8.7

2009-01-06T08:25:35Z

Thanks for you replies.
I set the parallel port on EPP and it seems OK.
The memory is external SRAM(4 x KM736V987) in address 0x10000000 and CS1 is enabled for it in config file:

; Chip select CS1 - external synchronous burst RAM
writemem.l 0x2fc10c 0xFF800000      ; OR1=0xFF800000
                                                        ; BSCY 0x#######E = 0x0 - 0-clock burst beat length
                                                         ; SCY 0x######F# = 0x0 - (2+SCY)*clock = 0 wait
                                                         ; AM   0xFFFE#### = 0xFFF80000 - 512 kByte
                                                         ;                 = 0xFFF00000 -   1 MByte
                                                         ;                 = 0xFFE00000 -   2 MByte
                                                         ;                 = 0xFFC00000 -   4 MByte
                                                         ;                 = 0xFF800000 -   8 MByte
                                                         ;                 = 0xFF000000 - 16 MByte
writemem.l 0x2fc108 0x10000001       ; BR1=0x10000001
;writemem.l 0x2fc108 0x10000001        ; BR1=0x00000001 relocation to base address 0x0
                                                         ; Bit 0x#######1 = 1 - region valid
                                                         ; Bit 0x#######2 = 0 - burst access enabled
                                                         ; Bit 0xFFFF#### = 0x1000 - Base address = 0x10000000

I select connect from debug menu and system connected,then in debug>EPPC>fill memory window set:
Memory Type:32 bit
Memory address:0x10000000
Memory Size:100

and it writes to memory(I can view).But when I check it for Memory size 0x8000 makes error and every thing goes wrong.
I select the checkbox for 'verify memory writes',the verify fails.
PhyCORE has 4M SRAM and i don't know what make this errors?

Best Regards
Farzane

Re: Setting of parallel port

2009-01-05T08:50:05Z

I suspect the two PHYTEC documents were written at different times, by different authors, using different McCraigor BDM's. ECP and EPP is what I had used on older BDM's, so not sure on the comment saying to avoid those modes.

Quick glance at McCraigors web site points out the MPDemon is compatible with all types of parallel ports, but ECP and EPP are recommended for best performance. Also is a note that PCI to Parallel Port Cards will improve performance, which is recommended.

http://www.macraigor.com/downloads/MPDemon_manual.pdf

Some notebooks will mux the Parallel Port function with other devices, so do check that the Parallel Port Cable is full IEEE-1284 compliant. One 'trick' one laptops is to look for an open ground, so the Parallel Port becomes a floppy interface (some older laptops allowed for floppy devices to be attached).

Tom

---- F KH <farzane_kh@...> wrote:

> Hi,
>
> why the setting of parallel printer port in document number "L-524e.pdf" in phytec site and that in FAQ in "phytec GmbH(http://www.phytec.de/de/support/faq/faq-phycore-mpc555.html)" are different?which is correct?
>
> The question is "LPT-to-BDM interface for MPC555"
>
> Regards,
> F KH
>
>
>

RE: problem in running 'Hello_fl' example by codewarrior 8.7

2009-01-05T08:11:47Z

Keep the entry point at __start. When the debugger enters there, select
'mixed' mode so you can confirm if the source assembly is actually
stored. In addition, under target settings in the debugger portion,
select the checkbox for 'verify memory writes'. If the verify fails or
you don't see your disassembled code in the debugger, then the code is
not loading correctly - this is likely caused by having the linker
assemble to the wrong address.

On the subject of wrong address, please check you have memory at
0x10000000. This must be external RAM, correct? If so, please ensure
the config file is correctly setting up a chip select for this memory.

Maybe take a step back and try something easier i.e. under 'debug' tab,
select connect to test if the wiggler is correctly communicating with
the device. If it appears to connect, open a memory window at internal
RAM and test you can read an write data. I don't know exactly what the
connect does, but if it runs the config file, you should also be able to
read/write the external RAM at 0x10000000. If it doesn't execute the
config file, then view the registers and edit the BRx/ORx to enable the
chip select x until you get your memory setup correctly.

I am not familiatr with the board or project you are running - if its
external flash, you have to ensure your flash programmer is correctly
setup which is an additional step to aim for once you verify you can
connect.

- Allan

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of F KH
Sent: Friday, January 02, 2009 11:07 PM
To: MPC500@...
Subject: [MPC500] problem in running 'Hello_fl' example by codewarrior
8.7

Hi,
I'm trying to run Hello_Fl(latest version) example on a PHYCORE MPC555
with
CW8.7, but after making the project when I try to debug,an error
occurred(Could
not set PC on entry point).
I change the entry point of project in EPPC Linker(__start) to main but
it
doesn't work too.examine different states of debugger setting so,but
each time
the error occur ed.
I set my printer port on normal mode and use MSIWiggler(Parallel port)
and
everything in setting page is default or set by example project.
Some times it goes through and make an powerpc exception error:
'powerpc exception
machine check exception 0X200'
I think the addresses of the project aren't correct.
{FPU Buffer address :0x10000000
Code address :0x10002000
Stack Address :0x100FFFF0 }
Thanks in advance for all your replies.

F.Kh

[Non-text portions of this message have been removed]

Setting of parallel port

2009-01-04T21:55:18Z

Hi,

why the setting of parallel printer port in document number "L-524e.pdf" in phytec site and that in FAQ in "phytec GmbH(http://www.phytec.de/de/support/faq/faq-phycore-mpc555.html)" are different?which is correct?

The question is "LPT-to-BDM interface for MPC555"

Regards,
F KH

problem in running 'Hello_fl' example by codewarrior 8.7

2009-01-02T21:07:14Z

Hi,
I'm trying to run Hello_Fl(latest version) example on a PHYCORE MPC555 with
CW8.7, but after making the project when I try to debug,an error occurred(Could
not set PC on entry point).
I change the entry point of project in EPPC Linker(__start) to main but it
doesn't work too.examine different states of debugger setting so,but each time
the error occur ed.
I set my printer port on normal mode and use MSIWiggler(Parallel port) and
everything in setting page is default or set by example project.
Some times it goes through and make an powerpc exception error:
'powerpc exception
machine check exception 0X200'
I think the addresses of the project aren't correct.
{FPU Buffer address   :0x10000000
Code address           :0x10002000
Stack Address        :0x100FFFF0   }
Thanks in advance for all your replies.

F.Kh

(unknown)

2009-01-02T21:01:42Z

Hi,
I'm trying to run Hello_Fl(latest version) example on a PHYCORE MPC555 with CW8.7, but after making the project when I try to debug,an error occurred(Could not set PC on entry point).
I change the entry point of project in EPPC Linker(__start) to main but it doesn't work too.examine different states of debugger setting so,but each time the error occur ed.
I set my printer port on normal mode and use MSIWiggler(Parallel port) and everything in setting page is default or set by example project.
Some times it goes through and make an powerpc exception error:
'powerpc exception
machine check exception 0X200'
I think the addresses of the project aren't correct.

{FPU Buffer address   :0x10000000
Code address           :0x10002000
  Stack Address        :0x100FFFF0 }

Thanks in advance for all your replies.

F.Kh

RE: Startup of MPC5500 (MPC5566)

2008-12-30T12:48:00Z

I'm not sure what could be causing this, some questions and comments
below, maybe you have already solved it since you posted this.

- which debugger are you using?

- is it possible the debugger init script is doing something
significant? Try removing as much as possible and see if it still runs.

- could it be an SRAM ECC error i.e. related to above, is the debugger
initializing the SRAM? One test for this is to try running without the
debugger after first running with the debugger but without a power
cycle. Or an easier way is just to try removing the SRAM init from the
debuggr init script.

- could it be a power up issue? Try a reset after power has stabilised
without th debugger.

- most wigglers connect to the 3.3V line. Look at the 3.3V with and
without the wiggler connected to see if there is any significant change.

- you could try using the free GAP debugger from Freescale. Its a
simple tool but is good because its simple i.e. its easier to determine
exactly what the debugger is doing.

- what happens without the debugger? Can you confirm the clkout is at
correct frequency? I recollect that the watchdog should also be firing
a reset periodically i.e. possible every 20 seconds or so.

- Allan

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of stevenaschroeder
Sent: Monday, December 22, 2008 2:40 PM
To: MPC500@...
Subject: [MPC500] Startup of MPC5500 (MPC5566)

I'm just bringing up our first MPC5566 board. Everything is fine with
a debugger. I watch the BAM find the RCHW, jumps to my code, and runs
fine. (I just have a loop wiggling a GPIO--geesh.) Without the
debugger, however, I get nothing.

Can someone point me in the right direction--what I am missing?

Thanks,
Steve

[Non-text portions of this message have been removed]

(unknown)

2008-12-22T23:00:06Z

Hi,

I'm trying to run Hello_Fl(latest version) example on a PHYCORE MPC555 with CW8.7, but after making the project when I try to debug,an error occurred(Could not set PC on entry point).
I change the entry point of project in EPPC Linker(__start) to main but it doesn't work too.examine different states of debugger setting so,but each time the error occur ed.
I set my printer port on normal mode and use MSIWiggler(Parallel port) and everything in setting page is default or set by example project.
Please help me, what do I do.

Thanks in advance for all your replies.

F.Kh

Namal Kumara is out of the office.

2008-12-22T13:03:52Z

I will be out of the office starting 12/18/2008 and will not return until
01/12/2009.

I will check mail occasionally but will have limited ability to respond.
If you need immediate assistance or information please contact Chris
Gillanders.

Robert F Semrau is out of the office.

2008-12-22T13:01:16Z

I will be out of the office starting 12/18/2008 and will not return until
01/05/2009.

I will respond to your message when I return.

Startup of MPC5500 (MPC5566)

2008-12-22T12:39:42Z

I'm just bringing up our first MPC5566 board. Everything is fine with
a debugger. I watch the BAM find the RCHW, jumps to my code, and runs
fine. (I just have a loop wiggling a GPIO--geesh.) Without the
debugger, however, I get nothing.

Can someone point me in the right direction--what I am missing?

Thanks,
Steve

RE: MPC565 hanging at temperature

2008-11-24T09:22:58Z

Thank you Allan,

I did check through earlier posts looking for clues, but didn't come up
with anything. Our PU resistors are 1K on both PORESET, HRESET and
SRESET.

We let the unit cool down and it starts up again. I've looked at the RSR
and no PO reset has occurred but both EHRS and SWRS have occurred. We
don't know though whether the watchdog reset is the cause or effect.
I.e. which one occurred first.

Regards
Pete

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of Dobbin Allan
Sent: 24 November 2008 15:54
To: MPC500@...
Subject: RE: [MPC500] MPC565 hanging at temperature

I remember previous posts about he the value of the HRESET resistor i.e.
reducing from 10K to 4.7k or 1k. Could you please search previous posts
forthis and see if it gives any improvement? What value of R are you
using?

- Allan

________________________________

From: MPC500@... <mailto:MPC500%40yahoogroups.com>
[mailto:MPC500@... <mailto:MPC500%40yahoogroups.com> ] On
Behalf
Of Pete James
Sent: Monday, November 24, 2008 5:14 AM
To: MPC500@... <mailto:MPC500%40yahoogroups.com>
Subject: [MPC500] MPC565 hanging at temperature

Hi all,

We have a problem with a MPC566 based ECU. We have manufactured several
batches of this product with no problems. The latest batch freeze at
temperatures over 80 degrees C. The MPC566 part is an MZ part so should
be good for 125 degrees.

We have checked all the supplies and they are correct.

PORESET is stable (not asserted)
HRESET is flicking up and down - presumably causing the reset of the
part, and generated internally

When the ambient temperature falls below 80 degrees the part runs
normally again. We have nothing connected to the HRESET line other than
the pull up resistor.

Any thoughts and help would be appreciated. It's baffling us as previous
batches have worked with no problems.

Best regards
Pete

Pete James
Technical Specialist/Chief Engineer - Electronics & Software
Prodrive
Kenilworth
Warwickshire
CV8 1NR
UK
DDI - +44 (0) 1676 536023
Email - pjames@... <mailto:pjames%40prodrive.com>
<mailto:pjames%40prodrive.com>

[Non-text portions of this message have been removed]

[Non-text portions of this message have been removed]

RE: MPC565 hanging at temperature

2008-11-24T07:54:27Z

I remember previous posts about he the value of the HRESET resistor i.e.
reducing from 10K to 4.7k or 1k. Could you please search previous posts
forthis and see if it gives any improvement? What value of R are you
using?

- Allan

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf
Of Pete James
Sent: Monday, November 24, 2008 5:14 AM
To: MPC500@...
Subject: [MPC500] MPC565 hanging at temperature

Hi all,

We have a problem with a MPC566 based ECU. We have manufactured several
batches of this product with no problems. The latest batch freeze at
temperatures over 80 degrees C. The MPC566 part is an MZ part so should
be good for 125 degrees.

We have checked all the supplies and they are correct.

PORESET is stable (not asserted)
HRESET is flicking up and down - presumably causing the reset of the
part, and generated internally

When the ambient temperature falls below 80 degrees the part runs
normally again. We have nothing connected to the HRESET line other than
the pull up resistor.

Any thoughts and help would be appreciated. It's baffling us as previous
batches have worked with no problems.

Best regards
Pete

Pete James
Technical Specialist/Chief Engineer - Electronics & Software
Prodrive
Kenilworth
Warwickshire
CV8 1NR
UK
DDI - +44 (0) 1676 536023
Email - pjames@... <mailto:pjames%40prodrive.com>

[Non-text portions of this message have been removed]

MPC565 hanging at temperature

2008-11-24T03:14:09Z

Hi all,

We have a problem with a MPC566 based ECU. We have manufactured several
batches of this product with no problems. The latest batch freeze at
temperatures over 80 degrees C. The MPC566 part is an MZ part so should
be good for 125 degrees.

We have checked all the supplies and they are correct.

PORESET is stable (not asserted)
HRESET is flicking up and down - presumably causing the reset of the
part, and generated internally

When the ambient temperature falls below 80 degrees the part runs
normally again. We have nothing connected to the HRESET line other than
the pull up resistor.

Any thoughts and help would be appreciated. It's baffling us as previous
batches have worked with no problems.

Best regards
Pete

Pete James
Technical Specialist/Chief Engineer - Electronics & Software
Prodrive
Kenilworth
Warwickshire
CV8 1NR
UK
DDI - +44 (0) 1676 536023
Email - pjames@...

RE: Access denied

2008-11-14T07:33:55Z

Alan,

Thank you verify much for your help!

Alas, this only confirm my fears: we left RSTCONF unconnected on our new board :-(( The old one had an external pull-up resistor to +3.3V and it would have been easy to drive it low. Next rework of this new card will include a pull-up...

Best regards.

Jean-Christophe MATHAE

CIRTEM
http://www.cirtem.com

bâtiment Pointe Bleue
20, voie l'Occitane
BP661
31319 LABEGE cedex
France

________________________________

De : MPC500@... [mailto:MPC500@...] De la part de Dobbin Allan
Envoyé : vendredi 14 novembre 2008 16:16
À : MPC500@...
Objet : RE: [MPC500] Access denied

Reset configuration comes from block 0 shadow flash - if certain bits in the shadow reset config word is programmed to 0, BDM can be locked out. To get the part back, drive RSTCONF LOW to override the shadow config. The reset config is now sampled from the data bus and chances are that is all you will have to do. If you have certain DATA pins held low, you may have to pull those up. Its been a while since I worked on that part and I can't remember exactly what the relevant bits are, but this is likely enough to get you by.

Assuming BDM now works, erase the shadow and you should be able to use the part again as normal.

- Allan

________________________________

From: MPC500@... <mailto:MPC500%40yahoogroups.com> [mailto:MPC500@... <mailto:MPC500%40yahoogroups.com> ] On Behalf Of Jean-Christophe MATHAE
Sent: Friday, November 14, 2008 4:38 AM
To: MPC500@... <mailto:MPC500%40yahoogroups.com>
Subject: [MPC500] Access denied

Hello,

While trying to use the General Market CMF Driver for MPC555, I think that I have turned a MPC555 chip into a useless bit of silicon...

Is this possible? Could a wrong shadow information in Flash make the chip unresponsive to the BDM?

Best regards.

Jean-Christophe MATHAE

CIRTEM
http://www.cirtem.com <http://www.cirtem.com> <http://www.cirtem.com <http://www.cirtem.com> >

bâtiment Pointe Bleue
20, voie l'Occitane
BP661
31319 LABEGE cedex
France

[Non-text portions of this message have been removed]

RE: Access denied

2008-11-14T07:00:55Z

Reset configuration comes from block 0 shadow flash - if certain bits in the shadow reset config word is programmed to 0, BDM can be locked out. To get the part back, drive RSTCONF LOW to override the shadow config. The reset config is now sampled from the data bus and chances are that is all you will have to do. If you have certain DATA pins held low, you may have to pull those up. Its been a while since I worked on that part and I can't remember exactly what the relevant bits are, but this is likely enough to get you by.

Assuming BDM now works, erase the shadow and you should be able to use the part again as normal.

- Allan

________________________________

From: MPC500@... [mailto:MPC500@...] On Behalf Of Jean-Christophe MATHAE
Sent: Friday, November 14, 2008 4:38 AM
To: MPC500@...
Subject: [MPC500] Access denied

Hello,

While trying to use the General Market CMF Driver for MPC555, I think that I have turned a MPC555 chip into a useless bit of silicon...

Is this possible? Could a wrong shadow information in Flash make the chip unresponsive to the BDM?

Best regards.

Jean-Christophe MATHAE

CIRTEM
http://www.cirtem.com <http://www.cirtem.com>

bâtiment Pointe Bleue
20, voie l'Occitane
BP661
31319 LABEGE cedex
France

[Non-text portions of this message have been removed]

Access denied

2008-11-14T02:37:51Z

Hello,

While trying to use the General Market CMF Driver for MPC555, I think that I have turned a MPC555 chip into a useless bit of silicon...

Is this possible? Could a wrong shadow information in Flash make the chip unresponsive to the BDM?

Best regards.

Jean-Christophe MATHAE

CIRTEM
http://www.cirtem.com

bâtiment Pointe Bleue
20, voie l'Occitane
BP661
31319 LABEGE cedex
France

Using TPU as UART?

2008-10-23T23:48:22Z

Hello,
When using tpu module a uart transmitter , how can we set firt
interrupt? I use a transmitting queue to send the bytes.
Thanks in advance
Coskun

Using TPU channel as serial output

2008-10-23T03:56:09Z

Hello,
When using tpu channels as serial (rs232) output, how can we set first sent byte interrupt? Do we have to send the first byte in the queue?
Thanks in advance
Coskun

mpc555 internal flash programming using GMD

2008-09-25T07:08:49Z

Hi All,

Since some days i have been trying to program the internal flash of my mpc555 using the motorola's general market CMF drivers. I have been successful in erasing the flash but when i try to program the flash using the parallel program driver function, i am getting an exception of type "Implementation-dependent software emulation" since the PC value goes to 0x1000.
Does anyone have any idea what could be the problem?
I am executing the program using the greenhills debugger in the RAM. I am working with mpc555 phyCORE development board which has 20MHz crystal oscillator.
Thanks.

- pat

Level 7 Interrupt

2008-09-22T11:32:12Z

We are seeing a level 7 interrupt on the MPC555 that can not be cleared.

Level 7 is masked and we can find no place where the code can generate
this interrupt.

Has anyone seen this problem or can anyone provide some clues?

Jim Cooper

ASYMTEK

jcooper@...

760-930-7242

[Non-text portions of this message have been removed]

Unexpected interrupt handler 1 problem

2008-09-04T22:47:22Z

Hi,

We are developing an embedded application using MPC565 and for testing
purpose we are using an PC based application which is used to monitor
the parameters of the system, communication is serial communication.

Whenever we are adding variables in the PC application for monitoring
purpose at one point we are getting Unexpected Interrupt Handler 1
problem. We are not able to locate the source of the problem with our
application as the stack status is shown to be inconsistent each time.

We tested the performance of serial communication using hyperterminal
application. There is no problem with the serial communication.

Also the PC based serial application is used similarly in other
applications without problems.

Can anyone please guide us to locate the problem.

Thanks and regards,
Veeresh P K

Query on PWM/DIO functionality

2008-07-30T03:42:30Z

Hi All,

We see that the pins MPIO32B11, MPIO32B12, MPIO32B5 and MPIO32B6 can
also be used as MPWM20, MPWM21, MPWM4 and MPWM5 respectively.

In one of our application we need to use MPIO32B11 and MPIO32B12 as
discrete inputs and MPIO32B5 and MPIO32B6 as PWM outputs.

However as per used manual all these pins can be either configured for
discrete or PWM functionality.

Is there is any way of using the pins configured as MPWM for reading
discrete inputs. Please advice.

Best regards,
Veeresh

New to Codewarrior of MPC555

2008-07-11T14:10:55Z

Hi everyone,

I am new to Code warrior MPC555 Edition 8.1v, so I was wondering if someone would help me in the programming process like the debugging, running n compiling part.

thank you
s_pinky

Interfacing ADC and DAC to MPC555

2008-07-11T11:19:05Z

Hi Everyone,

I am doing analog to digital conversion and digital to analog conversion with the MPC555. I am using external ADC(MAX188) and DAC(MAX536).I am having trouble, I was wondering if anyone has a sample code in C++ for this device.

Thanks in Advance

s_pinky

Re: Help for init value of SRAM in MPC 562

2008-07-02T16:11:13Z

Hi Sudhersan,

I'm not working with MPC500-series chips at the moment, but the usual
approach is to declare/use a "non-init" segment. Most compilers will
generate startup code that initialises all RAM apart from the non-init
segment.

I'm not sure of the details for doing this on your specific platform
(compiler, in particular). However, your compiler manual should
contain something on the subject.

As an alternative, you could tweak the startup code itself to skip a
certain location(s). Not recommended, but often done.

Geoff

--- In MPC500@..., Sudhersan Lal <sudhersanl@...> wrote:
>
> Hello Everyone
> Anybody know or can help me to find out more information regarding
the initialization value of SRAM contents during power up .
> I would like to save some values in sram so that I can read that
back after a reset , for eg saving a byte value and its compliment
and check the consistency between these two variables . This would
make sure that, the value is really what I saved prior to reset and
not the garbage value which would appear in the memory after a power up.
> Any existing behavior known for mpc microcontrollers related to this?
> if it is stored like the value and its compliment , what is the
probability of the random initial values in two bytes to be compliment
of each other and mistaken as the good value
> Regards
> Sudhersan

RE: Help for init value of SRAM in MPC 562

2008-07-02T08:55:49Z

It is definitely possible to find different values in SRAM at power-on. Some are more common than others, but short power outages can change just a few bits.

I would suggest using a 32 bit CRC rather than a single inverted byte. That greatly reduces the chances of an error not being detected (although still not zero).

Randall Young
Sr Software Engineer
Navcom Technology, Inc.
A John Deere Company

> -----Original Message-----
> From: MPC500@... [mailto:MPC500@...] On Behalf Of
> Sudhersan Lal
> Sent: Tuesday, July 01, 2008 8:43 PM
> To: MPC500@...
> Subject: [MPC500] Help for init value of SRAM in MPC 562
>
> Hello Everyone
> Anybody know or can help me to find out more information regarding the
> initialization value of SRAM contents during power up .
> I would like to save some values in sram so that I can read that back
> after a reset , for eg saving a byte value and its compliment and check
> the consistency between these two variables . This would make sure that,
> the value is really what I saved prior to reset and not the garbage value
> which would appear in the memory after a power up.
> Any existing behavior known for mpc microcontrollers related to this?
> if it is stored like the value and its compliment , what is the
> probability of the random initial values in two bytes to be compliment of
> each other and mistaken as the good value
> Regards
> Sudhersan
>

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