LPC Bus Interface

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LPC Bus Interface

by ahsoon :: Rate this Message:

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are there any LPC bus interface vhdl code for spartan 3E fpga?
 
Im trying to make one to tap the keyboard's traffic. I'm using the LPC 33Mhz clock to do the processing. Managed to get something from there, but it doesnt seem right.
 
My LFRAME never seems to be activated no matter what I do. Anyone has any idea?


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Re: LPC Bus Interface

by Mark McDougall :: Rate this Message:

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ahsoon wrote:

> Im trying to make one to tap the keyboard's traffic. I'm using the LPC
> 33Mhz clock to do the processing. Managed to get something from there,
> but it doesnt seem right.
>
> My LFRAME never seems to be activated no matter what I do. Anyone has
> any idea?

I can't really help you much, other than to say what you're attempting
should be doable. I had success with a VHDL module to tap the LPC bus for
firmware reads, driven off the LPC clock.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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Parent Message unknown Re: LPC Bus Interface

by ahsoon :: Rate this Message:

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Mind lending me your eyes for a while?

my codes is here http://www.savefile.com/files/1655664

Im not sure if it is my sampling that is wrong or my fifo or is it my
uart. I ran on modelsim my sampling+fifo..and the output of fifo is
right. I ran my uart on it's own and it's able to transmit.

 But i'm having problem simulating all of them together...

----- Original Message -----
From: Mark McDougall<markm@v...>
To:
Date: Wed Jul  9 07:35:44 CEST 2008
Subject: [oc] LPC Bus Interface

> ahsoon wrote:
>
> > Im trying to make one to tap the keyboard's traffic. I'm using
> the LPC
> > 33Mhz clock to do the processing. Managed to get something
> from there,
> > but it doesnt seem right.
> >
> > My LFRAME never seems to be activated no matter what I do.
> Anyone has
> > any idea?
> I can't really help you much, other than to say what you're
> attempting
> should be doable. I had success with a VHDL module to tap the LPC
> bus for
> firmware reads, driven off the LPC clock.
> Regards,
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266
>
>
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